This invention relates to a multiprocessor cratecontroller which could be used in the automation of systems and the making of scientific instruments.
A microprocessor cratecontroller, which contains a microprocessor, a program, and internal storage connected through interface circuits, containing a CAMAC strobe generator, a CAMAC instruction register and a block for CAMAC zero address instruction control--with the CAMAC bus, is known. Data transfer between the CAMAC bus and the storage of the cratecontroller is realized by means of a 3K 8-bits storage, as 1K 24-bits word storage. The microprocessor uses 8-bits per cycle from this storage array, the CAMAC bus directly exchanging 24-bits words per cycle.
This type of solution is convenient for a high-data rate in the transfer between modules and the microprocessor, but raises difficulties in real-time processing, because of the high-level time consumption for the transfer of the content of the one variable. It is an inefficient mode for the storage, because 24-bits words are not always used in the data transfer.
The use of 3 by 8 logical gates is the other known and often used way of realization of data transfer on the bus. This mode is slower, but more to be preferred for input-output operations because of a high-data rate in real-time processing.
The defects of the known microprocessor cratecontrollers are the low speed of the storage cycle, the fixed priority levels of the stations of the crate, software interruption handling, which still raises the time of the storage cycle; finally, the specific modes and data-blocks transfer is software realized.